PIC18F4682T-I/ML【PDF 55/183 页】IC PIC MCU FLASH 40KX16 44QFN

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PIC18F46J50 FAMILY

DS39931D-page 148

2011 Microchip Technology Inc.

10.6

PORTE, TRISE and LATE

Registers

Depending on the particular PIC18F46J50 family

device selected, PORTE is implemented in two

different ways.

For 44-pin devices, PORTE is a 3-bit wide port. Three

pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/

AN7/PMCS) are individually configurable as inputs or

outputs. These pins have Schmitt Trigger input buffers.

When selected as analog inputs, these pins will read as

‘0’s.

The corresponding Data Direction register is TRISE.

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e., put the corresponding output

driver in a High-Impedance mode). Clearing a TRISE

bit (= 0) will make the corresponding PORTE pin an

output (i.e., put the contents of the output latch on the

selected pin).

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

The Data Latch register (LATE) is also memory

mapped. Read-modify-write operations on the LATE

PORTE.

EXAMPLE 10-6:

INITIALIZING PORTE

Each of the PORTE pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is per-

formed by setting bit, REPU (PORTE<6>). The weak

pull-up is automatically turned off when the port pin is

configured as an output. The pull-ups are disabled on a

POR. The integrated weak pull-ups consist of a semi-

conductor structure similar to, but somewhat different,

from a discrete resistor. On an unloaded I/O pin, the

weak pull-ups are intended to provide logic high indica-

tion, but will not necessarily pull the pin all the way to

VDD levels.

Note that the pull-ups can be used for any set of

features, similar to the pull-ups found on PORTB

Note:

PORTE is available only on 44-pin devices.

Note:

On a POR, RE<2:0> are configured as

analog inputs.

CLRF

LATE

;Initialize LATE output

;latch values

MOVLB

0x0F

;ANCON registers not

;in access bank

BSF

ANCON0,PCFG5

;RE0/AN5 as digital

BSF

ANCON0,PCFG6

;RE1/AN6 as digital

MOVLW

0x03

;Example value used to

;initialize data direction

MOVWF

TRISE

;RE0, RE1 as inputs

;RE2 as output

REGISTER 10-5:

PORTE REGISTER

R/W-0

U-0

R/W-0

RDPU

REPU

—

RE2

RE1

RE0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

RDPU:

PORTD Pull-up Enable bit

= PORTD pull-ups are enabled by individual TRIS values

= All PORTD pull-ups are disabled

bit 6

REPU:

PORTE Pull-up Enable bit

= PORTE pull-ups are enabled by individual TRIS values

= All PORTE pull-ups are disabled

bit 5-3

Unimplemented:

Read as ‘0’

bit 2-0

RE<2:0>:

PORTE Data Input bits

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